1. Field of the Invention
The present invention relates to a semiconductor memory which requires periodic refresh operations to retain data written in its memory cells. In particular, the present invention relates to a semiconductor memory which performs refresh operations automatically inside without requiring a refresh command from exterior. In addition, the present invention relates to a technology for testing the foregoing semiconductor memory.
2. Description of the Related Art
In recent years, mobile apparatuses such as a cellular phone have become more sophisticated in service facilities, and the amounts of data to be handled have been growing steadily. Higher capacities are then required of the work memories to be mounted on the mobile apparatuses accordingly.
Conventionally, the work memories of the mobile apparatuses have used SRAMs which allow easier system configuration. The SRAMs are, however, greater than DRAMs in the number of devices for constituting each single bit of cell, and thus are disadvantageous for higher capacities. In view of this, semiconductor memories that have DRAM memory cells and operate as SRAMs by performing refresh operations on the memory cells automatically inside have been developed.
In the semiconductor memories of this type, the refresh operation time for performing a single refresh operation is included in the read cycle time or write cycle time. Specifically, the first half of a cycle time is allocated for the refresh operation time. The actual read operation or write operation is performed in the second half of the cycle time. Thus, the systems (users) on which the semiconductor memories are mounted need not be aware of the refresh operations in the semiconductor memories. That is, the users can use these semiconductor memories as SRAMs.
Besides, in the semiconductor memories of this type, the refresh operation time is rendered shorter than the read operation time for the sake of reducing the cycle time. Specifically, the time for selecting word lines in a refresh operation is shorter than the time for selecting word lines in a read operation (for example, see Japanese Examined Patent Application Publication No. 7-58589 (pp. 2–3, FIG. 4)).
In the semiconductor memory disclosed in the foregoing publication, a refresh operation is performed before a read operation when a refresh request occurs immediately before the read operation. The refresh operation time is set to be shorter than the read operation time. The refresh operation time, however, can only be made slightly shorter than the read operation time in order to rewrite predetermined signal quantities of data to the memory cells. As described above, an actual read operation is performed in the second half of the read cycle time. Consequently, it is impossible to reduce the access time sufficiently.
Incidentally, FIG. 4 of the foregoing publication does not show that refresh operations RF are performed before and after a read operation (read data D). What is shown in FIG. 4 is a simplified example where the refresh operation RF is performed before or after the read operation in accordance with the timing of occurrence of the refresh request (lines 1–10 in column 5 of the foregoing publication).
Moreover, as stated above, the pseudo SRAMs perform refresh operations automatically without being recognized from exterior. In the meantime, the data retained in the memory cells might be corrupted unless refresh operations are performed properly. It is therefore necessary to evaluate if refresh operations are performed properly. In particular, detailed evaluations are required of the circuit operation when a conflict occurs between a request for a read operation or write operation which is supplied from exterior and a request for a refresh operation which occurs inside the chips.